IC Verification · AI Tooling

AI meets Silicon

I'm Chen, an IC verification engineer. I build AI tools for chip design verification, and I write about what that actually looks like in practice.

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Chen Ben Haroosh
5+yrs verif

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Projects

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HSI Debug Agent

An AI agent that turns hours of manual HSI regression triage into minutes — pulling register mismatches from logs, cross-referencing a 10,000-row spec database, and tracking changes across two independent time axes: spec snapshots and regression history.

AIAgentsHSIPythonVerification

Python Regression Automation GUI Tool

A PyQt GUI tool that cut regression setup time by 70% and boosted coverage by 30% by replacing error-prone manual config file editing with a visual interface.

PythonPyQtAutomationUVMVerification

Reactive Slave UVM Environment for SPI EEPROM Verification

A UVM-based reactive slave UVC that replaced a pre-verified RTL EEPROM model in our SoC verification environment, enabling error injection and improved controllability.

UVMSystemVerilogVerificationSPIEEPROM

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Blog

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The Third Suspect

2026-08-23

I needed a SystemVerilog simulator an AI agent could drive, so I built a UVM environment for an open-source NoC router and fixed the six things that broke in the simulator underneath. On an open stack, a failing test has three suspects, not two.

UVMSystemVerilogSVANoCVerilatorEDAAI

// about me

From chips to intelligence

5+ years in IC verification. Now I build LLM-based tools that live inside that same workflow: UVM, C++, EDA.

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