IC Verification · AI Research

AI meets Silicon

I'm Chen — an IC verification engineer building AI systems that make chip design faster, smarter, and more reliable. This is where I share my projects, experiments, and findings.

View Projects Read the Blog

10+ yrs

IC verification

AI × EDA research

Based in Israel

// featured work

Projects

All projects

HSI Debug Agent

An AI agent that turns hours of manual HSI regression triage into minutes — pulling register mismatches from logs, cross-referencing a 10,000-row spec database, and tracking changes across two independent time axes: spec snapshots and regression history.

AIAgentsHSIPythonVerification

Python Regression Automation GUI Tool

A PyQt GUI tool that cut regression setup time by 70% and boosted coverage by 30% by replacing error-prone manual config file editing with a visual interface.

PythonPyQtAutomationUVMVerification

Reactive Slave UVM Environment for SPI EEPROM Verification

A UVM-based reactive slave UVC that replaced a pre-verified RTL EEPROM model in our SoC verification environment, enabling error injection and improved controllability.

UVMSystemVerilogVerificationSPIEEPROM

A Simple'ish UVM Testbench For a SDRAM Controller

A UVM testbench built around an open-source 16-bit SDRAM controller, exploring SDRAM architecture, timing constraints, and burst operations through hands-on verification.

UVMSystemVerilogVerificationSDRAMOpen Source

// about me

From chips to intelligence

10+ years in IC verification, now applying AI to make the chip design process smarter. I work at the intersection of EDA tooling, LLMs, and formal methods.

More about me