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Field notes from silicon
Essays, tutorials, and half-formed thoughts on AI × IC verification.
Published when something feels worth saying — never on a schedule.
AI is Reshaping Hardware Verification: Insights from Siemens' Vision
Discover how AI is transforming hardware verification in 2025, as discussed by Abhi Kolpekwar (VP at Siemens) on “The DV Digest” podcast. Explore the evolving role of verification engineers, the impact of artificial intelligence on EDA tools, and the real-world shift from hype to practical results in chip design and testing.
The Canaries Are Singing: What Stanford's AI Employment Study Means for Hardware Engineers
Stanford study reveals AI is already displacing young developers while older engineers thrive. As a verification engineer using AI tools daily, here's what this means for hardware careers.
The Verification Gap: Why AI Still Struggles with Hardware Testing
Every verification engineer I've talked with since this AI thing started has told me the same thing: It's far from excellent. And honestly, it looked like if you don't write fullstack JavaScript or Python, ChatGPT or Claude's code generation will be pretty awful.
The Motivation Dip: Why Good Ideas Lose Their Shine (And How I Push Through)
I've been there more times than I'd like to admit. I start a new project with fire in my belly – every small win feels electric, every line of code or sketch on paper brings me closer to something amazing. The idea consumes my thoughts, drives my weekends, makes me wake up excited. Then reality […]
Remote Debugging CocoTB and PyUVM Tests with VSCode
Learn how to set up remote debugging for CocoTB and PyUVM hardware verification tests using VSCode and debugpy. This step-by-step guide shows you how to inspect variables, set breakpoints, and step through PyUVM code execution while running tests on a remote machine.
Asynchronous Programming in PyUVM and Cocotb: Building Concurrent Hardware Verification Environments
While traditional UVM uses SystemVerilog's concurrent constructs (fork-join, always, etc.), Python's async/await syntax provides a cleaner and more explicit approach to concurrency. This is particularly valuable in hardware verification, where we constantly need to model parallel processes, handle timing, and manage complex interactions between components.
Transitioning from SV/UVM to pyUVM: A Practical Guide – Part 2
In Part 1, we explored the fundamental components of pyUVM and how they compare to traditional SystemVerilog UVM. We covered transactions, drivers, monitors, coverage, and scoreboards. In Part 2, we dive deeper into test execution flow and advanced features that make pyUVM a powerful alternative to SystemVerilog UVM.
Transitioning from SV/UVM to pyUVM: A Practical Guide – Part 1
Part 1 of my 2-part guide on transitioning from SystemVerilog UVM to pyUVM. Compare verification components like transactions, drivers, and scoreboards with real TinyALU examples. Learn how Python features simplify verification workflows for modern engineers. Continue to Part 2 for advanced features.
Getting Started with Cocotb: Hardware Verification Made Easy
This is the first in a series of tutorials exploring Python-based hardware verification. As someone with experience in SystemVerilog UVM, I'm investigating whether Python-based verification frameworks like Cocotb and PyUVM offer advantages over traditional approaches. Join me on this journey as I learn, experiment, and share my findings. In this post, we'll set up Cocotb and run our first testbench. In the next post, we'll explore PyUVM.
Breaking Free from uvm_config_db: Embracing the Full Power of UVM Resources
Throughout my verification career, I've consistently used uvm_config_db as my go-to mechanism for sharing data between components in UVM testbenches. After reading Cliff Cummings' illuminating paper on UVM Resources, I've come to realize I've been limiting myself unnecessarily.
The State of IC/ASIC Verification in 2024: Promise and Pitfalls
The recently released 2024 Wilson Research Group Functional Verification Study offers a fascinating window into the world of IC/ASIC design and verification. As chips become increasingly complex and integrated into every aspect of our digital lives, understanding the verification landscape is crucial for industry professionals, investors, and technology enthusiasts alike.
a UVM Testbench for Out-of-Order Transaction Verification
In modern SoC designs, transaction routing through multiple paths is a common scenario. When the same transaction can take different routes with variable delays, ensuring data consistency becomes challenging. This blog post explores a UVM testbench architecture designed to verify out-of-order transaction handling while maintaining correct ordering for transactions with matching IDs.